1. Field of the Invention
The present invention relates generally to nonvolatile semiconductor memory devices, and more particularly to electrically programmable read-only memories of the type in which a read voltage or a verify voltage is essentially equivalent in temperature dependency characteristic to threshold voltages of memory cells therein.
2. Description of the Background
Nonvolatile semiconductor memory devices are becoming more widely used in the manufacture of digital equipment, particularly computers, as the speed and cost advantages of such devices increase. As the memories require higher packing density, higher speed, and lower power dissipation, reliability becomes more critical.
Nonvolatile memories include read-only memories (ROMs). Prior known ROMs are designed to employ two different kinds of threshold voltages Vt1, Vt2 for memory-cell transistors causing them to correspond to a "1" and a "0" for binary data being stored therein. In this case, the threshold voltage Vt of a memory cell may be represented by EQU Vt=Vfb+X{2.phi..times.Fn.times.(2.phi.-Vbs)+g.times.Fs(2.phi.-Vbs)}.sup.1/2 ,
where Vfb is the flat-band voltage (this is proportional to the difference ".phi.-ms" in work function between the gate and the silicon substrate used in the memory cell), X is the polarity of channel ("+1" when the channel is of the n conductivity type; "-1" when p type), .phi. is the Fermi potential, Fn is the correction coefficient for the "narrow channel" effect, Vbs is the potential difference between the substrate and the source, g is the back-bias effect coefficient, and Fs is the short-channel effect correction coefficient. Normally, the threshold voltage may be changed or switched between the two different potentials by changing the value of .phi.-ms due to alteration of the dose of channel implantation.
During read operations, the gate potential Vg of a memory cell is set at a certain level midway between the two threshold voltages (Vt1&lt;Vt2). Assume that a memory cell having the threshold voltage Vt1 is selected for read. In this case, a corresponding cell transistor is rendered conductive causing a drain current to flow therein. Assuming on the other hand that a memory cell with the threshold voltage Vt2 is selected for read, its cell transistor is rendered nonconductive hindering the flow of drain current. Accordingly, data may be read by sensing whether such drain current attempts to flow in such selected cell.
Generally, as temperature varies, the gate-to-substrate work function difference .phi.-ms and Fermi potential .phi. will vary with the result of the memory-cell threshold value being also changed in potential accordingly. In contrast, the gate potential applied for read operations will not vary with temperature because of the fact that the gate potential is a power supply voltage or a voltage divided therefrom. Hence, any indeterminate data will no longer be read erroneously even when the threshold voltage varies due to temperature variations; consequently, it has been required that the two kinds of threshold voltages be established with a sufficient difference being predefined therebetween. In other words, a greater margin should be strictly required for the threshold values of cells.
Unfortunately, such "greater threshold value margin" approach does not come without accompanying a serious problem, especially on occasions where the power supply voltage accidentally drops in potential or in the case where an attempt is made to increase the magnitude of information per unit cell by letting a memory cell exhibit more than three kinds of threshold voltages.
FIG. 7 shows one prior known read voltage generator circuit, which is a voltage divider circuitry including two resistors R17, R18 for resistive division of an input voltage. FIG. 8 depicts a graphic representation for explanation of the threshold voltage margin, wherein solid lines are used to designate the distribution of threshold voltages at room temperature, and dotted lines indicate the same at high temperatures. As can be readily seen from viewing the graph, the threshold value tends to decrease in potential as the temperature increases. Due to this, even if the read margin has been optimized at room temperature, when the temperature increases, the resulting minimum value of higher threshold voltage Vt2 decreases to "escape" from the margin region; this results in that the actual read margin becomes smaller than the inherently expected margin.
Electrically rewritable nonvolatile semiconductor memories such as electrically erasable programmable read only memories (EEPROMs) are known. The EEPROMs have an array of memory cells fabricated on a silicon substrate, each of which employs a metal oxide semiconductor field effect transistor (MOSFET), i.e., an MOS structure with an electrically isolated gate commonly referred to as the floating gate for storage of electrical carriers, and a control gate overlying the charge storage gate. Typically, with such EEPROMs, data-writing or "programming" is carried out by application of a specific potential higher than the power supply voltage to a presently selected one of the memory cells during write operations thus controlling the charge amount on the charge storage layer (i.e., floating gate) by use of a variety of mechanisms such as avalanche injection, channel injection, tunneling, etc., depending on the construction of the cells. The selected cell will change in threshold value due to the resulting charge amount on its charge storage layer; accordingly, the cell can be selectively at one of the two threshold voltages (Vt1&lt;Vt2). During erase operations, all the data are set at one threshold voltage (Vt1, by way of example) with a predefined bit length as a unit. Write or program operations are made selectively with respect to every bit: the threshold voltage of a selected cell is forced to be at Vt2, whereas those of the remaining, nonselected ones are kept at Vt1.
In the MOS-EEPROMs it is also required that memory cells being erased or ones programmed be substantially uniform in threshold value among cells. To attain this, the "verify read" operations are inevitable to verify that the programming and erasing operations have been performed properly with respect to either a cell bit or a block of cells concerned, while the programming is done for every bit, the erasing of the entire array or a block of individual memory cells may be accomplished. In this situation, during write-verify operations for example, a voltage Vvrfy higher than the ordinary read voltage Vread is specifically applied to the gate of a selected cell transistor to ensure that a sufficiently wide margin remains between the two kinds of threshold voltages therein.
Also in the MOS-EEPROMs, the memory-cell threshold voltage varies in potential with temperature as in the case of ROMs discussed previously; however, the read voltage and verify voltage are substantially independent of any possible temperature variations. In view of this fact, it has been strictly required that the two kinds of threshold values be so set as to allow a sufficient difference to remain therebetween. Especially in EEPROMS, such threshold-voltage margin should be much greater than that in ROMs. One reason for this is that it will possibly happen that the temperature decreases during application of the verify voltage Vvrfy, for instance, and increases during application of the ordinary read voltage Vread. In addition, this "wide threshold-voltage margin" scheme will raise a more serious problem on occasions where power supply happens to potentially drop accidentally as in ROMs, or in case where an attempt is made to increase the information storage amount per memory cell by letting cells exhibit more than three kinds of threshold voltage levels.
As has been discussed above, it is required that the prior art nonvolatile semiconductor memory devices, including ROMs and EEPROMs be greater in threshold-voltage margin to "absorb" any possible variations of cell transistors in threshold voltage with changes in ambient temperature, which in turn leads to a serious bar to achievement of low-voltage drive and multiple value data storage memory architectures.